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ATmega128
Table 62. Clock Select Bit Description
CSn2
0
0
0
0
1
1
1
1
CSn1
0
0
1
1
0
0
1
1
CSn0
0
1
0
1
0
1
0
1
Description
No clock source. (Timer/Counter stopped)
clk I/O /1 (No prescaling
clk I/O /8 (From prescaler)
clk I/O /64 (From prescaler)
clk I/O /256 (From prescaler)
clk I/O /1024 (From prescaler)
External clock source on Tn pin. Clock on falling edge
External clock source on Tn pin. Clock on rising edge
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
Timer/Counter1
Control Register C –
Bit
7
6
5
4
3
2
1
0
TCCR1C
Read/ W rite
Initial Value
FOC1A
W
0
FOC1B
W
0
FOC1C
W
0
–
R
0
–
R
0
–
R
0
–
R
0
–
R
0
TCCR1C
Timer/Counter3
Control Register C –
Bit
7
6
5
4
3
2
1
0
TCCR3C
Read/ W rite
Initial Value
FOC3A
W
0
FOC3B
W
0
FOC3C
W
0
–
R
0
–
R
0
–
R
0
–
R
0
–
R
0
TCCR3C
? Bit 7 – FOCnA: Force Output Compare for Channel A
? Bit 6 – FOCnB: Force Output Compare for Channel B
? Bit 5 – FOCnC: Force Output Compare for Channel C
The FOCnA/FOCnB/FOCnC bits are only active when the W GMn3:0 bits specifies a non-P W M
mode. W hen writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare
match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed
according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are imple-
mented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the
effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare Match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnB bits are always read as zero.
? Bit 4:0 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be written to zero when TCCRnC is written.
136
2467X–AVR–06/11
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